Power gating is a technique used in integrated circuit design to reduce power consumption. Power gating is commonly used in integrated circuit memory arrays to reduce standby or leakage power by shutting off current to blocks of the memory that are not in use.
Early implementations of power gating use a constant threshold voltage drop across a power gating device to temporarily deactivate a portion of a circuit. These so-called diode-connected implementations provide sufficient power savings in larger technology nodes (e.g., 45 nm, 32 nm, 22 nm) where leakage increases exponentially with supply voltage. However, in newer technology nodes where leakage is more linearly related to supply voltage, the diode-connected implementations do not deliver sufficient power savings. For example, a diode-connected power gating scheme used in a memory array with 22 nm devices provides a 200 mv voltage drop of array power supply, which corresponds to a 53% leakage reduction for pull-up/pull-down and a 49% total bitcell leakage reduction. On the other hand, a similar diode-connected power gating scheme used in a memory array with 14 nm finFET technology provides only a 20% leakage reduction for pull-up/pull-down and a 15% total bitcell leakage reduction.